Methods Of Forming Isolation Structures, And Methods Of Forming Nonvolatile Memory

ABSTRACT

Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500° C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700° C. to about 1000° C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another.

TECHNICAL FIELD

Methods of forming isolation structures, and methods of formingnonvolatile memory.

BACKGROUND

The fabrication of semiconductor-based circuitry comprises formation ofhighly integrated electrical components (with example electricalcomponents being transistors, resistors and capacitors), and thuscomprises forming electrical components in close proximity to eachother. Insulative materials may be used to electrically isolate variouselectrical components from one another.

One method of electrically isolating adjacent electrical components fromone another is to use trench isolation. Trench isolation may be formedby creating trenches in a semiconductor material, and then filling thetrenches with insulative material.

One type of insulative material that may be used to fill the trenches issilicon oxide formed from spin-on dielectric (SOD). Example SODs arepolysilazanes. When polysilazanes are utilized as SODs, the formation ofsilicon oxide may comprise multiple steps. Initially, spin-onmethodology may be used to fill trenches with polysilazane.Subsequently, the polysilazane within the trenches may be converted tosilicon oxide by exposing the polysilazane to oxidant and appropriatethermal conditions.

A common method for converting a polysilazane to silicon oxide is to usesteam densification. Specifically, the polysilazane is exposed to steamwhile being maintained at a temperature of at least 585° C.

A problem with such steam densification is that oxidant can penetratethrough the polysilazane and into semiconductor material adjacent thepolysilazane. Thus, it is common to provide a silicon nitride linerwithin the trenches prior to filling the trenches with polysilazane. Thesilicon nitride liner can function as a barrier during steamdensification of the polysilazane, with such barrier protectingunderlying semiconductor material from oxidation during the steamdensification.

In some applications it would be desirable to utilize SODs, but to omitthe silicon nitride barriers. Accordingly, it would be desirable todevelop new methods for utilizing SODs during fabrication of isolationstructures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-7 are diagrammatic cross-sectional views of a portion of asemiconductor construction at various steps of an example embodimentmethod.

FIGS. 8 and 9 illustrate alternative processing steps that may followthe processing step of FIG. 7.

FIG. 10 illustrates an example processing step that may follow theprocessing step of FIG. 8.

FIG. 11 illustrates an example processing step that may follow theprocessing step of FIG. 9.

FIG. 12 is a simplified block diagram of a memory system in accordancewith an embodiment.

FIG. 13 is a schematic diagram of a nonvolatile memory array inaccordance with an embodiment.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

In some embodiments, the invention includes new methods for convertingpolysilazane into silicon oxide. The new methods may include steamtreatment at a relatively low temperature (for instance, underconditions in which the temperature of the polysilazane does not exceed500° C.), for a relatively long time (for instance, for time of fromabout two hours to about 10 hours) to convert the polysilazane tosilicon oxide; followed by an anneal of the silicon oxide under an inertambient to a maximum temperature of at least about 700° C. to densifythe silicon oxide. The low-temperature steam treatment and subsequentanneal may be mild enough to allow silicon nitride barrier layers of theprior art to be omitted, and yet may form silicon dioxide suitable forelectrically isolating integrated circuit devices from one another.

The omission of the silicon nitride layers that may be accomplishedutilizing methodology of the present invention can be particularlyadvantageous for applications containing nonvolatile memory cells (forinstance, NAND applications). Specifically, the silicon nitride barrierlayers of prior art trench isolation structures can problematicallydegrade nonvolatile memory device performance through thecharge-trapping characteristics that are inherent in silicon nitride.Methodology of the present invention may be used to eliminate thesilicon nitride barrier layers of prior art trench isolation structures,and thus can avoid problems associated with the inherent charge-trappingcharacteristics of such silicon nitride barrier layers.

Example methods of the present invention is described with reference toFIGS. 1-11.

Referring to FIG. 1, such shows a portion of a semiconductorconstruction 10. The semiconductor construction includes a semiconductormaterial 12 having a patterned mask 14 thereover.

Semiconductor material 12 may, for example, comprise, consistessentially of, or consist of monocrystalline silicon lightlybackground-doped with appropriate p-type dopant. In some embodiments,the semiconductor material 12 may be referred to as a semiconductorsubstrate. The terms “semiconductive substrate” and “semiconductorsubstrate” mean any construction comprising semiconductive material,including, but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” meansany supporting structure, including, but not limited to, thesemiconductive substrates described above. In some embodiments,semiconductor material 12 may be considered to correspond to asemiconductor substrate ultimately utilized to support integratedcircuitry.

Patterned mask 14 comprises a plurality of spaced apart features 16,with each of the features having a layer 20 supported over a layer 18.In some embodiments, layers 20 and 18 may be floating gate material andtunnel dielectric material, respectively. In such embodiments, layer 20may comprise, consist essentially of, or consist of silicon (forinstance, polysilicon); and layer 18 may comprise, consist essentiallyof or consist of silicon dioxide. In some embodiments, layers 20 and 18may be a hard mask and a pad layer, respectively. In such embodiments,layer 20 may comprise, consist essentially of, or consist of siliconnitride; and layer 18 may comprise, consist essentially of, or consistof silicon dioxide.

Layers 18 and 20 may be formed into the shown pattern of mask 14 byinitially forming layers 18 and 20 entirely across an upper surface ofsemiconductor material 12, utilizing a photolithographically-patternedphotoresist mask (not shown) to define the pattern that is to be formedinto layers 18 and 20, utilizing etching to transfer the pattern fromthe photoresist mask into layers 18 and 20, and then removing thephotoresist mask to leave the construction of FIG. 1.

The patterned mask 14 has a plurality of openings 22, 24, 26, 28 and 30extending therethrough. The openings 24, 26, 28 and 30 are all about thesame width as one another in the shown cross-section. In contrast, thewidth of opening 22 is larger than the widths of openings 24, 26, 28 and30. In some embodiments, opening 22 may define a boundary between amemory array region and another region peripheral to the memory arrayregion. A dashed line 23 is provided to diagrammatically delineate aboundary between the memory array region and the peripheral region; andspecifically is shown delineating a boundary between a memory arrayregion 32 on the right side of the dashed line, and a peripheral region34 on the left side of the dashed line.

Referring to FIG. 2, openings 22, 24, 26, 28 and 30 are extended intosemiconductor material 12 with an etch selective for material 12relative to materials 18 and 20. Each of the openings 22, 24, 26, 28 and30 within semiconductor material 12 has a periphery. Specifically,opening 22 has a periphery 32 comprising a bottom 31 and a pairsidewalls 33; opening 24 has a periphery 34 comprising a bottom 35 andsidewalls 37; opening 26 has a periphery 34 comprising a bottom 39 andsidewalls 41; opening 28 has a periphery 38 comprising a bottom 43 andsidewalls 45; and opening 30 has a periphery 40 comprising a bottom 47and sidewalls 49. The bottoms and sidewalls of the peripheriescorrespond to semiconductor material 12, and accordingly in someembodiments may consist of monocrystalline silicon.

In some embodiments, the openings 22, 24, 26, 28 and 30 may correspondto trenches that extend in and out of the page relative to thecross-section of FIG. 2.

Referring to FIG. 3, oxide liners 42 are formed along the peripheries32, 34, 36, 38 and 40 of the openings 22, 24, 26, 28 and 30,respectively. The oxide liners may be formed by utilizing an oxidant tooxidize the semiconductor material 12 exposed within the openings; andin some embodiments may correspond to so-called “native oxide” formed byexposing semiconductor material 12 to O₂. In embodiments in whichsemiconductor material 12 consists of silicon, the oxide liners mayconsist of silicon dioxide. The oxide liners 42 are optional, andaccordingly may be omitted in some embodiments.

Although the oxide liners 42 are shown formed only along semiconductormaterial 12, in other embodiments the oxidation conditions utilized toform the oxide liners may be sufficient to oxidize surfaces of layer 20.

Referring to FIG. 4, a layer of oxide 44 is deposited acrossconstruction 10 and within openings 22, 24, 26, 28 and 30. In someembodiments, layer 44 may correspond to silicon dioxide depositedutilizing tetraethylorthosilicate (TEOS). Oxide 44 is optional, andaccordingly may be omitted in some embodiments. Also, although oxide 44is shown formed after oxide 42, in other embodiments oxide 44 may firstbe deposited, and then oxidation conditions may be chosen which diffuseoxidant through oxide 44 and thereby oxidize the semiconductor material12 underlying deposited material 44.

Referring to FIG. 5, polysilazane 46 is deposited over construction 10and within openings 22, 24, 26, 28 and 30. The polysilazane maycorrespond to a spin-on dielectric, and accordingly may be depositedutilizing spin-on methodologies. Polysilazanes contain Si, N and H.Example polysilazanes that can be used are hexamethyldisilazane,tetramethyldisilazane, octamethylcyclotetrasilazine,hexamethylcyclotrisilazine, diethylaminotrimethylsilane,dimethylaminotrimethylsilane and perhydro-polysilazane.Perhydro-polysilazane may be preferred in some embodiments.

A notable aspect of FIG. 5 is that there is no silicon nitride barrierlayer between polysilazane 46 and the peripheries 32, 34, 36, 38 and 40of openings 22, 24, 26, 28 and 30. In other words, there is no siliconnitride layer separating the polysilazane within the openings from thesemiconductor material 12 along the peripheries of such openings.

Referring to FIG. 6, polysilazane 46 (FIG. 5) is converted to siliconoxide 48 by exposure of the polysilazane to steam. The silicon oxide hasthe formula SiO_(x), where x is greater than zero and less than or equalto 2. The exposure to the steam may comprise subjecting the polysilazaneto a maximum temperature that does not exceed 500° C. for a sufficient aduration of time to convert all of the polysilazane to silicon oxide. Insome embodiments, the maximum temperature may be within a range of fromabout 350° C. to about 500° C., and the time duration may be from abouttwo hours to about 10 hours (with longer durations being utilized forlower maximum temperatures). The polysilazane temperature may beincreased to the maximum temperature utilizing any suitable temperaturegradient. In some embodiments, the temperature gradient may compriseonly temperature changes within the polysilazane (and the rest ofconstruction 10) of less than or equal to 10° C./minute. If thetemperature gradient changes a temperature of construction 10 tooquickly, defects may be introduced into some regions of theconstruction. The utilization of a temperature gradient comprising onlytemperature changes of less than 10° C./minute may eliminate suchdefects. The polysilazane may be exposed to steam during the time thatthe temperature is ramped to the maximum temperature, as well as duringthe time that the temperature is maintained at the maximum temperature.

The exposure of the polysilazane to steam may occur in any suitablereaction chamber, and at any suitable pressure. In some embodiments, thepressure may be approximately atmospheric pressure.

Referring to FIG. 7, the silicon oxide 48 (FIG. 6) is subjected to ananneal to convert such silicon oxide to densified silicon oxide 50. Theannealing may be conducted under an inert atmosphere (in other words,while construction 10 is exposed to a gas that is non-reactive with theconstruction, with suitable gases including one or more of argon, heliumand N₂). The annealing may utilize a maximum annealing temperature thatis at least about 700° C.; and in some embodiments may utilize a maximumannealing temperature that is within a range of from at least 700° C. toless than or equal to about 1000° C. The annealing may be conducted atany suitable pressure, and in some embodiments is conducted at aboutatmospheric pressure.

The maximum annealing temperature may be held for any suitable durationof time. In some embodiments, the maximum annealing temperature may beheld for a time duration that is within a range of from about 1 minuteto about two hours. In some embodiments, the annealing may comprise notonly the duration that the maximum annealing temperature is held, butalso a period of time during which a temperature of construction 10 isramped up to the maximum annealing temperature, and then ramped backdown from the maximum annealing temperature to about room temperature;and the construction may be under the inert atmosphere during theentirety of the time that the construction is being ramped to and fromthe maximum annealing temperature.

The ramping of the temperature of construction 10 to and from themaximum annealing temperature may comprise a gradient having onlytemperature changes of less than 10° C./minute, for reasons similar tothose discussed above regarding the temperature gradient utilized toramp construction 10 during the steam treatment.

The annealing of the silicon oxide may occur in the same reactionchamber utilized for the steam treatment of the polysilazane, or mayoccur in a different reaction chamber than that utilized for the steamtreatment. If the annealing and steam treatment are conducted in thesame reaction chamber, then the annealing can follow directly after thesteam treatment (in other words, without breaking a seal to thechamber). In some embodiments, an atmosphere within the chamber can beswitched from the steam conditions to an inert gas without coolingconstruction 10, and then the temperature of the construction can beramped from the steam treatment temperature to the maximum annealingtemperature.

If the annealing and steam treatment are conducted in different reactionchambers from one another, than the silicon oxide formed by the steamtreatment (oxide 48 of FIG. 6) may be cooled to room temperature priorto initiation of the temperature ramp utilized for the annealing; or, inother embodiments, may be subjected to the annealing without firstcooling the construction to room temperature.

In embodiments in which the layers 18 and 20 are a pad layer and a hardmask, respectively, such layers may be removed from over semiconductormaterial 12 with planarization. For instance, FIG. 8 shows construction10 after the construction has been subjected to planarization (forinstance, chemical-mechanical polishing) to remove material 50, layer 18and layer 20 from over semiconductor material 12, and to form aplanarized upper surface 51 extending across semiconductor material 12,and the oxides 42, 44 and 50 within openings 22, 24, 26, 28 and 30. Theoxides 42, 44 and 50 form a plurality of isolation structures 52, 54,56, 58 and 60 within the openings 22, 24, 26, 28 and 30, respectively.Such isolation structures may correspond to shallow trench isolation(STI) in some embodiments. The isolation structures 52, 54, 56, 58 and60 contain no silicon nitride between oxide 50 and semiconductormaterial 12, which can avoid some of the problems discussed aboveregarding silicon nitride barrier layers.

As mentioned above, either or both of oxides 42 and 44 may be optional,and accordingly some embodiments comprise isolation structurescontaining oxide 50 either alone, or in combination with only one of theshown oxides 42 and 44.

In embodiments in which layers 18 and 20 (FIG. 7) comprise tunneldielectric material and floating gate material, respectively,planarization may be used to remove materials 44 and 50 from over layer20, while leaving the layers 18 and 20 remaining over construction 10;and thus to form a construction of the type shown in FIG. 9. Theconstruction of FIG. 9 has a planarized upper surface 53 extendingacross materials 20, 44 and 50. Only the memory array region 32 is shownin FIG. 9 (rather than also showing the peripheral region 34 (FIG. 7)),in order to simplify the drawing.

The constructions of FIGS. 8 and 9 may be subjected to subsequentprocessing to form nonvolatile memory. FIG. 10 shows a nonvolatilememory gate stack formed relative to the construction of FIG. 8, andFIG. 11 shows nonvolatile memory gates formed relative to theconstruction of FIG. 9.

Referring to FIG. 10, a memory gate stack 62 is formed over planarizedupper surface 51. The memory gate stack comprises tunnel dielectric 64,charge storage material 66, dielectric material 68, and control gatematerial 70. The tunnel dielectric 64 may comprise any suitablecomposition, and in some embodiments may comprise, consist essentiallyof, or consist of silicon dioxide. The charge storage material 66 maycomprise any suitable composition. In some embodiments, the chargestorage material may comprise polycrystalline silicon (in other words,may comprise a floating gate material). In other embodiments, the chargestorage material may comprise charge trapping material, such as, forexample, silicon nitride and/or nanoparticles. The dielectric material68 may comprise any suitable composition, and in some embodiments maycomprise one or more of silicon dioxide, hafnium oxide and zirconiumoxide. The control gate material 70 may comprise any suitablecomposition, and in some embodiments may comprise one or more of variousmetals, metal-containing compounds, and conductively-doped semiconductormaterials.

FIG. 11 shows a processing stage following that of FIG. 9 in anembodiment in which layer 18 comprises tunnel dielectric material, andin which layer 20 comprises floating gate material. Dielectric material68 and control gate material 70 are formed over floating gate materialof layer 20 to form a plurality of nonvolatile memory gates. Thedielectric material 68 and control gate material 70 of FIG. 11 may beformed in lines that extend in and out of the page relative to thecross-sectional view of FIG. 11.

The nonvolatile memory gates of FIG. 11 may be incorporated intononvolatile memory devices that are isolated from one another byisolation structures comprising densified oxide 50. Similarly, the gatestack 62 of FIG. 10 may be subsequently patterned to form a plurality ofgates for nonvolatile memory devices (for instance, gates of NANDdevices) over memory array region 32, with at least some of such gatesbeing electrically isolated from one another by the isolation structures54, 56, 58 and 60.

In some embodiments, the nonvolatile memory gates formed with thevarious processing steps of FIGS. 1-11 may correspond to string gatesand/or select gates. FIGS. 12 and 13 describe example configurations andapplications of nonvolatile memory devices.

FIG. 12 is a simplified block diagram of a memory system 500. The memorysystem includes an integrated circuit flash memory device 502 (e.g., aNAND memory device), that includes an array of memory cells 504, anaddress decoder 506, row access circuitry 508, column access circuitry510, control circuitry 512, input/output (I/O) circuitry 514, and anaddress buffer 516. Memory system 500 also includes an externalmicroprocessor 520, or other memory controller, electrically connectedto memory device 502 for memory accessing as part of an electronicsystem. The memory device 502 receives control signals from theprocessor 520 over a control link 522. The memory cells are used tostore data that is accessed via a data (DQ) link 524. Address signalsare received via an address link 526, and are decoded at address decoder506 to access the memory array 504. Address buffer circuit 516 latchesthe address signals. The memory cells may be accessed in response to thecontrol signals and the address signals.

FIG. 13 is a schematic of an array 200 of memory cells. Such may be aportion of memory array 504 of FIG. 10, and may correspond to a NANDarray of memory cells. Memory array 200 includes access lines, such aswordlines 202 ₁ to 202 _(N), and intersecting local datalines, such asbitlines 204 ₁ to 204 _(M). The number of wordlines 202 and the numberof bitlines 204 may be each some power of two, for example, 256wordlines and 4,096 bitlines. The local bitlines 204 may be coupled toglobal bitlines (not shown) in a many-to-one relationship.

Memory array 200 includes strings 206 ₁ to 206 _(M). Each stringincludes nonvolatile charge-storage transistors 208 ₁ to 208 _(N). Thecharge-storage transistors may use floating gate material to storecharge, or may use charge-trapping material (such as, for example,metallic nanodots) to store charge.

The charge-storage transistors 208 are located at intersections ofwordlines 202 and local bitlines 204. The charge-storage transistors 208of each string 206 are connected in series source to drain between asource select gate 210 and a drain select gate 212. Each source selectgate 210 is controlled by a source select line 214, while each drainselect gate 212 is controlled by a drain select line 215.

A source of each source select gate 210 is connected to a common sourceline 216. The drain of each source select gate 210 is connected to thesource of the first charge-storage transistor 208 of the correspondingstring 206. For example, the drain of source select gate 210 ₁ isconnected to the source of charge-storage transistor 208 ₁ of thecorresponding string 206 ₁. The source select gates 210 are connected tosource select line 214.

The drain of each drain select gate 212 is connected to a local bitline204 for the corresponding string at a drain contact 228. For example,the drain of drain select gate 212 ₁ is connected to the local bitline204 ₁ for the corresponding string 206 ₁ at drain contact 228 ₁. Thesource of each drain select gate 212 is connected to the drain of thelast charge-storage transistor 208 of the corresponding string 206. Forexample, the source of drain select gate 212 ₁ is connected to the drainof charge-storage transistor 208 _(N) of the corresponding string 206 ₁.

Charge-storage transistors 208 include a source 230, a drain 232, acharge storage node 234, and a control gate 236. Charge-storagetransistors 208 have their control gates 236 coupled to a wordline 202.A column of the charge-storage transistors 208 are those transistorswithin a string 206 that are coupled to a given local bitline 204. A rowof the charge-storage transistors 208 are those transistors commonlycoupled to a given wordline 202.

The embodiments discussed above may be utilized in electronic systems,such as, for example, computers, cars, airplanes, clocks, cellularphones, etc.

In compliance with the statute, the subject matter disclosed herein hasbeen described in language more or less specific as to structural andmethodical features. It is to be understood, however, that the claimsare not limited to the specific features shown and described, since themeans herein disclosed comprise example embodiments. The claims are thusto be afforded full scope as literally worded, and to be appropriatelyinterpreted in accordance with the doctrine of equivalents.

1. A method of forming an isolation structure, comprising: forming anopening extending into a semiconductor material; the opening having aperiphery comprising sidewalls and a bottom; providing a polysilazanewithin the opening, there being no silicon nitride-containing materialbetween the polysilazane and the periphery of the opening; exposing thepolysilazane to steam while not permitting a temperature of thepolysilazane to exceed about 500° C.; the exposure to the steamconverting the polysilazane to silicon oxide; and annealing the siliconoxide; the annealing comprising exposure of the silicon oxide to amaximum annealing temperature of at least about 700° C.
 2. The method ofclaim 1 wherein the temperature of the polysilazane is maintained withina range from about 350° C. to about 500° C. for a time of from about 2hours to about 10 hours during the exposure of the polysilazane to thesteam.
 3. The method of claim 1 wherein the maximum annealingtemperature is from about 700° C. to about 1000° C.
 4. The method ofclaim 1 wherein the annealing is conducted under an inert atmosphere. 5.The method of claim 1 wherein the annealing includes exposure of thesilicon oxide to a temperature gradient having only temperature changesof less than or equal to about 10° C./minute to ramp a temperature ofthe silicon oxide up to the maximum annealing temperature and down fromthe maximum annealing temperature.
 6. The method of claim 1 wherein theannealing occurs in a same chamber as the steam exposure; and whereinthe exposure of the silicon oxide to the temperature gradient comprisesramping the temperature of the silicon oxide up directly after the steamexposure, and without cooling of the silicon oxide after the steamexposure.
 7. The method of claim 1 wherein the annealing occurs in adifferent chamber than the steam exposure; and wherein the exposure ofthe silicon oxide to the temperature gradient comprises ramping thetemperature of the silicon oxide up from about room temperature to themaximum annealing temperature.
 8. The method of claim 1 wherein themaximum annealing temperature of the silicon oxide is maintained for atime of from at least about 1 minute to less than or equal to about 2hours.
 9. The method of claim 1 wherein the polysilazane isperhydro-polysilazane.
 10. The method of claim 1 wherein thepolysilazane is exposed to steam and to a temperature gradient havingonly temperature changes of less than or equal to about 10° C./minute toramp a temperature of the polysilazane up to the range of from about350° C. to about 500° C.
 11. The method of claim 1 further comprisingforming a silicon dioxide liner along the periphery of the opening priorto providing the polysilazane within the opening.
 12. The method ofclaim 11 wherein the forming of the silicon dioxide liner comprisesdeposition of the silicon dioxide along the sidewalls and bottom of theopening periphery.
 13. The method of claim 11 wherein: the semiconductormaterial is monocrystalline silicon; the opening extends into themonocrystalline silicon so that the sidewalls and bottom of the openingperiphery consist of the monocrystalline silicon; and the forming of thesilicon dioxide liner comprises oxidation of the monocrystalline siliconof the sidewalls and bottom of the opening periphery.
 14. A method offorming a plurality of isolation structures, comprising: forming apatterned mask over a semiconductor material; the mask defining aplurality of openings; extending the openings into the semiconductormaterial, each of the openings having a periphery along thesemiconductor material; providing a polysilazane within the openings,there being no silicon nitride-containing material between thepolysilazane and the semiconductor material along the peripheries of theopenings; exposing the polysilazane to steam while not permitting atemperature of the polysilazane to exceed about 500° C.; the exposure tothe steam converting all of the polysilazane to silicon oxide; andannealing the silicon oxide under an inert atmosphere; the annealingcomprising exposure of the silicon oxide to a temperature gradienthaving only temperature changes of less than or equal to about 10°C./minute to ramp a temperature of the silicon oxide up to a maximumannealing temperature and down from the maximum annealing temperature;the maximum annealing temperature being at least about 700° C.
 15. Themethod of claim 14 wherein the mask comprises a layer of floating gatematerial over a layer of tunnel dielectric material.
 16. The method ofclaim 14 wherein the mask comprises a layer of polysilicon over a layerof silicon dioxide.
 17. The method of claim 14 wherein the maskcomprises a layer of silicon nitride over a layer of silicon dioxide.18. The method of claim 14 wherein the annealing occurs in a samechamber as the steam exposure.
 19. The method of claim 14 wherein theannealing occurs in a different chamber than the steam exposure.
 20. Themethod of claim 14 wherein the polysilazane is perhydro-polysilazane.21. The method of claim 14 wherein the exposure to the steam includesexposure of the polysilazane to a temperature gradient having onlytemperature changes of less than or equal to about 10° C./minute to rampa temperature of the polysilazane up to a maximum steam treatmenttemperature.
 22. The method of claim 14 further comprising forming adeposition of silicon dioxide along the peripheries of the openingsprior to providing the polysilazane within the openings; and wherein thedeposition utilizes tetraethylorthosilicate.
 23. A method of formingnonvolatile memory, comprising: forming a plurality of isolationstructures extending into a semiconductor material; the forming of theisolation structures comprising providing polysilazane within trenchesin the semiconductor material, exposing the polysilazane to steam whilea temperature of the polysilazane does not exceed 500° C. to convert allof the polysilazane to silicon oxide, and annealing the silicon oxideunder an inert atmosphere at a temperature of at least about 700° C.; nosilicon nitride being between the polysilazane and peripheries of thetrenches; and forming a memory gate stack over the semiconductormaterial in regions between the openings; the memory gate stackincluding, in ascending order from the semiconductor material, tunneldielectric, charge storage material, dielectric material, and controlgate material.
 24. The method of claim 23 wherein the charge storagematerial is floating gate material.
 25. The method of claim 23 wherein:the charge storage material is floating gate material; and the chargestorage material and tunnel dielectric material are together utilized asa mask to define locations of the isolation structures.
 26. The methodof claim 23 wherein the charge storage material is charge trappingmaterial.
 27. The method of claim 23 wherein the annealing occurs in asame chamber as the steam exposure, and wherein the annealing isconducted immediately after the steam exposure and without cooling ofthe silicon oxide between the steam exposure and the annealing.
 28. Themethod of claim 23 wherein the annealing occurs in a different chamberthan the steam exposure.
 29. The method of claim 23 wherein thepolysilazane is perhydro-polysilazane.
 30. The method of claim 23wherein the polysilazane is exposed to steam and to a temperaturegradient having only temperature changes of less than or equal to about10° C./minute to ramp a temperature of the polysilazane up to a maximumsteam treatment temperature.
 31. The method of claim 23 furthercomprising exposing the silicon oxide to a temperature gradient havingonly temperature changes of less than or equal to about 10° C./minute toramp a temperature of the silicon oxide up to a maximum annealingtemperature.
 32. The method of claim 23 further comprising formingsilicon dioxide liners within the trenches prior to providing thepolysilazane within the trenches.